DRAM

DRAM

DRAM

DRAM

DRAM

MT4C4001J

MT4C4001J

Rev. 2.2 06/05

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

6

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < T

C

< 125°C; V

CC

= 5V ±10%)

PARAMETER

SYM

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Write command hold time

15

15

20

25

ns

Write command hold time (referenced to RAS\)

50

60

70

80

ns

Write command pulse width

15

15

20

25

ns

Write command to RAS\ lead time

20

20

25

30

ns

Write commend to CAS\ lead time

20

20

25

30

ns

Data-in setup time

0000

ns

22

Data-in hold time

12

15

18

25

ns

22

Data-in hold time (referenced to RAS\)

50

60

70

90ns

RAS\ to WE\ delay time

95

105

130

140

ns

21

Column address to WE\ delay time

60

65

80

90ns

21

CAS\ to WE\ delay time

45

45

55

60

ns

21

Transition time (rise or fall)

3

50

3

50

3

50

3

50

ns

Refresh period (1,024 cycles)

16

16

16

16

ms

RAS\ to CAS\ precharge time

0000

ns

CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH)

5

101010

ns

5

CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH)

10

15

20

25

ns

5

WE\ hold time (CAS\-BEFORE-RAS\ REFRESH)

10

10

10

10

ns

25, 28

WE\ setup time (CAS\-BEFORE-RAS\ REFRESH)

10

10

10

10

ns

25, 28

WE\ hold time (WCBR test cycle)

10

10

10

10

ns

25, 28

WE\ setup time (WCBR test cycle)

10

10

10

10

ns

25, 28

OE\ setup prior to RAS during HIDDEN REFRESH cycle

0000

ns

Output disable

15

20

25

25

ns

27

Output enable

15

20

25

25

ns

23

OE\ hold time from WE\ during READ-MODIFY-WRITE cycle

20

20

25

25

ns

26

-7

-8

-10

-12