Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADIS16362 Datasheet(PDF) 5 Page - Analog Devices

Part # ADIS16362
Description  Six Degrees of Freedom Inertial Sensor
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16362 Datasheet(HTML) 5 Page - Analog Devices

  ADIS16362 Datasheet HTML 1Page - Analog Devices ADIS16362 Datasheet HTML 2Page - Analog Devices ADIS16362 Datasheet HTML 3Page - Analog Devices ADIS16362 Datasheet HTML 4Page - Analog Devices ADIS16362 Datasheet HTML 5Page - Analog Devices ADIS16362 Datasheet HTML 6Page - Analog Devices ADIS16362 Datasheet HTML 7Page - Analog Devices ADIS16362 Datasheet HTML 8Page - Analog Devices ADIS16362 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 20 page
background image
ADIS16362
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Normal Mode
(SMPL_PRD ≤ 0x09)
Low Power Mode
(SMPL_PRD ≥ 0x0A)
Burst Read
Parameter
Description
Min1
Typ
Max
Min1
Typ
Max
Min1
Typ
Max
Unit
fSCLK
Serial clock
0.01
2.0
0.01
0.3
0.01
1.0
MHz
tSTALL
Stall period between data
9
75
1/fSCLK
μs
tREADRATE
Read rate
40
100
μs
t
CS
Chip select to clock edge
48.8
48.8
48.8
ns
tDAV
DOUT valid after SCLK edge
100
100
100
ns
tDSU
DIN setup time before SCLK rising edge
24.4
24.4
24.4
ns
tDHD
DIN hold time after SCLK rising edge
48.8
48.8
48.8
ns
tSCLKR, tSCLKF
SCLK rise/fall times
5
12.5
5
12.5
5
12.5
ns
tDR, tDF
DOUT rise/fall times
5
12.5
5
12.5
5
12.5
ns
tSFS
CS high after SCLK edge
5
5
5
ns
t1
Input sync positive pulse width
5
5
μs
tx
Input sync low time
100
100
μs
t2
Input sync to data ready output
600
600
μs
t3
Input sync period
833
833
μs
DIN
1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS
CS
SCLK
DOUT
1
2
3
4
5
6
15
16
R/W
A5
A6
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tDSU
tDHD
Figure 2. SPI Timing and Sequence
CS
tREADRATE
tSTALL
SCLK
Figure 3. Stall Time and Data Rate
t3
tX
t2
t1
SYNC
CLOCK (DIO4)
DATA
READY
Figure 4. Input Clock Timing Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com