MCP4728 datasheet(52/66 Pages) MICROCHIP

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MCP4728

DS22187C-page 52

7.1.1

DEVICE CONNECTION TEST

The user can test the presence of the MCP4728 device

on the I2C bus line without performing a data

conversion. This test can be achieved by checking an

acknowledge response from the MCP4728 device after

sending a read or write command. Figure 7-2 shows an

example with a read command:

Set the R/W bit “High” or “Low” in the address

byte.

Check the ACK pulse after sending the address

byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected,

otherwise it is not connected.

Send Stop bit.

FIGURE 7-2:

I2C Bus Connection Test.

7.2

Layout Considerations

Inductively-coupled AC transients and digital switching

noise from other devices can affect DAC performance

and DAC output signal integrity. Careful board layout

will minimize these effects. Bench testing has shown

that a multi-layer board utilizing a low-inductance

ground plane, isolated inputs, isolated outputs and

proper decoupling are critical to achieving good DAC

performance.

Separate digital and analog ground planes are

recommended. In this case, the VSS pin and the ground

pins of the VDD capacitors of the MCP4728 should be

terminated to the analog ground plane.

7.3

Power Supply Considerations

The power source should be as clean as possible. The

power supply to the device is used for both VDD and

DAC voltage reference by selecting VREF = VDD. Any

noise induced on the VDD line can affect DAC

performance. A typical application will require a bypass

capacitor in order to filter out high frequency noise on

the VDD line. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC

output. The bypass capacitor helps to minimize the

effect of these noise sources on signal integrity.

Figure 7-1 shows an example of using two bypass

capacitors (a 10 µF tantalum capacitor and a 0.1 µF

ceramic capacitor) in parallel on the VDD line. These

capacitors should be placed as close to the VDD pin as

possible (within 4 mm). If the application circuit has

separate digital and analog power supplies, the VDD

and VSS pins of the MCP4728 device should reside on

the analog plane.

7.4

Using Power Saving Feature

The device consumes very little power when it is in

Power-Down

(shut-down)

mode.

During

the

Power-Down mode, most circuits in the selected

channel are turned off. It is recommended to power

down any unused channel.

The device consumes the least amount of power if it

enters the Power-Down mode after the internal voltage

reference is disabled. This can be achieved by

selecting VDD as the voltage reference for all 4

channels and then issuing the Power-Down mode for

all channels.

7.5

Using Non-Volatile EEPROM

Memory

The user can store the I2C device address bits,

configuration bits and DAC input code of each channel

in the on-board non-volatile EEPROM memory using

the I2C write command. The contents of EEPROM are

readable and writable using the I2C command.

When the MCP4728 device is first powered-up or

receives General Call Reset Command, it uploads the

EEPROM contents to the DAC output registers

automatically and provides analog outputs immediately

with the saved settings in EEPROM. This feature is

very useful in applications where the MCP4728 device

is used to provide set points or calibration data for other

devices in the application systems. The MCP4728

device can save important system parameters when

the application system experiences power failure. See

Section 5.5 “Writing and Reading Registers and

EEPROM” for more details on using the non-volatile

EEPROM memory.

SCL

SDA

1A2 A1 A0 1

Start

Bit

Address Byte

Address bits

Device Code

R/W

Stop

Bit

MCP4728

Response

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