MFRC522 datasheet(31/96 Pages) NXP

31 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

31 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

8.6 Power reduction modes

8.6.1 Hard power-down

Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current

sinks including the oscillator. All digital input buffers are separated from the input pins and

clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or

LOW level.

8.6.2 Soft power-down mode

Soft Power-down mode is entered immediately after the CommandReg register’s

PowerDown bit is set to logic 1. All internal current sinks are switched off, including the

oscillator buffer. However, the digital input buffers are not separated from the input pins

and keep their functionality. The digital output pins do not change their state.

During soft power-down, all register values, the FIFO buffer content and the conﬁguration

keep their current contents.

After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down

mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately

clear it. It is cleared automatically by the MFRC522 when Soft power-down mode is

exited.

Remark: If the internal oscillator is used, you must take into account that it is supplied by

pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock

cycles can be detected by the internal logic. It is recommended for the serial UART, to ﬁrst

send the value 55h to the MFRC522. The oscillator must be stable for further access to

the registers. To ensure this, perform a read access to address 0 until the MFRC522

answers to the last read command with the register content of address 0. This indicates

that the MFRC522 is ready.

8.6.3 Transmitter power-down mode

The Transmitter Power-down mode switches off the internal antenna drivers thereby,

turning off the RF ﬁeld. Transmitter power-down mode is entered by setting either the

TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.

8.7 Oscillator circuit

Fig 22. Quartz crystal connection

001aak595

MFRC522

27.12 MHz

OSCOUT

OSCIN

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