MFRC522 datasheet(51/96 Pages) NXP

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MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

51 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.2.9

RxThresholdReg register

Selects thresholds for the bit decoder.

9.3.2.10

DemodReg register

Deﬁnes demodulator settings.

9.3.2.11

Reserved register 1Ah

Functionality is reserved for future use.

Table 69.

RxThresholdReg register (address 18h); reset value: 84h bit allocation

Bit

Symbol

MinLevel[3:0]

reserved

CollLevel[2:0]

Access

R/W

Table 70.

RxThresholdReg register bit descriptions

Bit

Symbol

Description

7 to 4

MinLevel

[3:0]

deﬁnes the minimum signal strength at the decoder input that will be

accepted

if the signal strength is below this level it is not evaluated

reserved

reserved for future use

2 to 0

CollLevel

[2:0]

deﬁnes the minimum signal strength at the decoder input that must be

reached by the weaker half-bit of the Manchester encoded signal to

generate a bit-collision relative to the amplitude of the stronger half-bit

Table 71.

DemodReg register (address 19h); reset value: 4Dh bit allocation

Bit

Symbol

AddIQ[1:0]

FixIQ

reserved

TauRcv[1:0]

TauSync[1:0]

Access

R/W

Table 72.

DemodReg register bit descriptions

Bit

Symbol

Value

Description

7 to 6

AddIQ

[1:0]

deﬁnes the use of I and Q channel during reception

Remark: the FixIQ bit must be set to logic 0 to enable the following

settings:

selects the stronger channel

selects the stronger channel and freezes the selected channel

during communication

reserved

FixIQ

if AddIQ[1:0] are set to X0b, the reception is ﬁxed to I channel

if AddIQ[1:0] are set to X1b, the reception is ﬁxed to Q channel

reserved

reserved for future use

3 to 2

TauRcv

[1:0]

changes the time-constant of the internal PLL during data reception

Remark: if set to 00b the PLL is frozen during data reception

1 to 0

TauSync

[1:0]

changes the time constant of the internal PLL during burst

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