MFRC522 datasheet(61/96 Pages) NXP

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MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

61 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.4.4

TestPinEnReg register

Enables the test bus pin output driver.

9.3.4.5

TestPinValueReg register

Deﬁnes the HIGH and LOW values for the test port D1 to D7 when it is used as I/O.

Table 122. TestSel2Reg register bit descriptions

Bit

Symbol

Value Description

TstBusFlip

test bus is mapped to the parallel port in the following order:

TstBusBit4,TstBusBit3, TstBusBit2, TstBusBit6, TstBusBit5,

TstBusBit0; see Section 16.1 on page 79

PRBS9

starts and enables the PRBS9 sequence according to ITU-TO150

Remark: all relevant registers to transmit data must be conﬁgured

before entering PRBS9 mode

the data transmission of the deﬁned sequence is started by the

Transmit command

PRBS15

starts and enables the PRBS15 sequence according to ITU-TO150

Remark: all relevant registers to transmit data must be conﬁgured

before entering PRBS15 mode

the data transmission of the deﬁned sequence is started by the

Transmit command

4 to 0 TestBusSel

[4:0]

selects the test bus; see Section 16.1 “Test signals”

Table 123. TestPinEnReg register (address 33h); reset value: 80h bit allocation

Bit

Symbol

RS232LineEn

TestPinEn[5:0]

reserved

Access

R/W

Table 124. TestPinEnReg register bit descriptions

Bit

Symbol

Value Description

RS232LineEn 0

serial UART lines MX and DTRQ are disabled

6 to 1 TestPinEn

[5:0]

enables the output driver on one of the data pins D1 to D7 which

outputs a test signal

Example:

setting bit 1 to logic 1 enables pin D1 output

setting bit 5 to logic 1 enables pin D5 output

Remark: If the SPI is used, only pins D1 to D4 can be used. If the

serial UART interface is used and the RS232LineEn bit is set to

logic 1 only pins D1 to D4 can be used.

reserved

reserved for future use

Table 125. TestPinValueReg register (address 34h); reset value: 00h bit allocation

Bit

Symbol

UseIO

TestPinValue[5:0]

reserved

Access

R/W

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