MFRC522 datasheet(58/96 Pages) NXP

58 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

58 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.3.11

TReloadReg register

Deﬁnes the 16-bit timer reload value.

Table 106. TModeReg register bit descriptions

Bit

Symbol

Value

Description

TAuto

timer starts automatically at the end of the transmission in all

communication modes at all speeds

if the RxModeReg register’s RxMultiple bit is not set, timer

stops immediately after receiving the ﬁrst data bit

if the RxMultiple bit is set to logic 1 the timer never stops, in

which case the timer can be stopped by setting the

ControlReg register’s TStopNow bit to logic 1

indicates that the timer is not inﬂuenced by the protocol

6 to 5

TGated[1:0]

internal timer is running in gated mode

Remark: in gated mode, the Status1Reg register’s TRunning

bit is logic 1 when the timer is enabled by the TModeReg

this bit does not inﬂuence the gating signal

non-gated mode

gated by pin MFIN

gated by pin AUX1

TAutoRestart

timer automatically restarts its count-down from the 16-bit

timer reload value instead of counting down to zero

timer decrements to 0 and the ComIrqReg register’s

TimerIRq bit is set to logic 1

3 to 0

TPrescaler_Hi

[3:0]

deﬁnes the higher 4 bits of the TPrescaler value

the following formula is used to calculate ftimer:

where 13.56 is the carrier frequency in MHz; for detailed

description, see Section 8.5 “Timer unit”

Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation

Bit

Symbol

TPrescaler_Lo[7:0]

Access

R/W

Table 108. TPrescalerReg register bit descriptions

Bit

Symbol

Description

7 to 0

TPrescaler_Lo[7:0] deﬁnes the lower 8 bits of the TPrescaler value

the following formula is used to calculate ftimer:

where 13.56 is the carrier frequency in MHz; for detailed

description, see Section 8.5 “Timer unit”

timer

13.56

TPrescaler

---------------------------------------

timer

13.56

TPrescaler

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