PCF2119AUSLASH2DASLASH2 datasheet(43/79 Pages) NXP

43 / 79 page

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

43 of 79

NXP Semiconductors

PCF2119x

LCD controllers/drivers

• Arbitration: procedure to ensure that if more than one master simultaneously tries to

control the bus, only one is allowed to do so and the message is not corrupted.

• Synchronization: procedure to synchronize the clock signals of two or more devices.

Fig 31. Master transmits to slave receiver; write mode

mgk899

011101

slave address

CONTROL BYTE A

DATA BYTE

CONTROL BYTE A

R/W

update

data pointer

1 byte

≥ 0 bytes

DATA BYTE

acknowledgement

from PCF2119x

Last data byte is a dummy byte (may be omitted).

Fig 32. Master reads after setting word address; writes word address, set RS; Read_data

mgg003

S 011101

0 A

slave address

CONTROL BYTE A

DATA BYTE

CONTROL BYTE A

R/W

update

data pointer

update

data pointer

1 byte

≥ 0 bytes

n bytes

last byte

≥ 0 bytes

DATA BYTE(1)

acknowledgement

DATA BYTE

SLAVE

ADDRESS

DATA BYTE

acknowledgement

no acknowledgement

R/W

PCF2119AU/2DA/2 Datasheet(PDF) 43 Page - NXP Semiconductors

PCF2119AU/2DA/2 Datasheet(HTML) 43 Page - NXP Semiconductors

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