PCF2119FUSLASH2SLASHF2 datasheet(42/79 Pages) NXP

42 / 79 page

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

42 of 79

NXP Semiconductors

PCF2119x

LCD controllers/drivers

11.2.1 I2C-bus protocol

One I2C-bus slave address is reserved for the PCF2119x (see Figure 30).

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the START procedure.

The I2C-bus conﬁguration for the different PCF2119x read and write cycles is shown in

Figure 31 to Figure 33.

The slow down feature of the I2C-bus protocol (receiver holds SCL line LOW during

internal operations) is not used in the PCF2119x.

11.2.2 I2C-bus deﬁnitions

Deﬁnitions:

• Transmitter: the device which sends the data to the bus.

• Receiver: the device which receives the data from the bus.

• Master: the device which initiates a transfer, generates clock signals and terminates a

transfer.

• Slave: the device addressed by a master.

• Multi-master: more than one master can attempt to control the bus at the same time

without corrupting the message.

Fig 29. Acknowledgement on the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Fig 30. PCF2119x I2C-bus slave address

011101

slave address

R/W

013aaa143

PCF2119FU/2/F2 Datasheet(PDF) 42 Page - NXP Semiconductors

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