PCF2119FUSLASH2SLASHF2 datasheet(5/79 Pages) NXP

5 / 79 page

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

5 of 79

NXP Semiconductors

PCF2119x

LCD controllers/drivers

7.2 Pin description

Table 3.

Pin description

Symbol

Description

VDD1

1 to 6

supply voltage 1 (logic)

VDD2

7 to 14

[1] supply voltage 2 (for high voltage generator)

VDD3

15 to 18

[1] supply voltage 3 (for high voltage generator)

E19

[2] data bus clock input

• set HIGH to signal the start of a read or write operation

• data is clocked in or out of the chip on the negative edge

of the clock

T1 and T2

20 and 21

test pins

• must be connected to VSS1

VSS1

22 to 29

[3] ground supply voltage 1

• for all circuits, except of high voltage generator

VSS2

30 to 35

[3] ground supply voltage 2

• for high voltage generator

VLCDSENSE

input for voltage multiplier regulation circuitry and for the bias

level generation

• if VLCD is generated internally then this pin must be

connected to VLCDOUT and VLCDIN

• if VLCD is generated externally then this pin must be

connected to VLCDIN only

VLCDOUT

37 to 43

VLCD output

• if VLCD is generated internally then this pin must be

connected to VLCDIN and to VLCDSENSE

• if VLCD is generated externally then this pin must be left

open-circuit

VLCDIN

44 to 49

input for LCD bias level generator

dummy

[4] -

R8 to R1,

R17,

R17DUP,

R18,

R9 to R16

51 to 58,

59,

100

141,

142 to 149

LCD row driver output

• R17 has two pins: R17 and R17DUP

• R17 and R18 drive the icons

C80 to C41,

C40 to C1

60 to 99,

101 to 140

LCD column driver output

dummy

150

[4] -

SCL

151 and 152

[5] I2C-bus serial clock input

153

test pin

• open-circuit

• not user accessible

POR

154

external Power-On Reset (POR) input

155

power-down mode select

• for normal operation pin PD must be LOW

SDA

156 and 157

[5] I2C-bus serial data input/output

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