33784 datasheet(12/30 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33784

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

voltage rises above the signal threshold, the counter

measures the time the bus is above the signal threshold.

When the bus voltage falls below the signal threshold again,

the first bit is finished and the next bit begins. The process is

repeated for each bit in the command.

The decoder interprets the bit as a logic [0] if the bus spent

more time below the signal threshold than above it.

Conversely, the decoder interprets the bit as a logic [1] if the

bus spent more time above the signal threshold than below it.

The advantage to this method of communication is that it will

accept data over a wide range of data rates and it is not

dependent on an accurate clock. A logic [0] is typically

indicated by spending 2/3 of the total bit time low, and a

logic [1] is typically indicated by spending 2/3 of the total bit

time high.

The command ends when the bus voltage rises above the

frame threshold and returns to the idle state.

Each threshold comparator has hysteresis to help to filter

noise on the bus during the transitions. There is also a filter,

which issues a reset if the bus remains below the frame

threshold for longer than the timeout limit. This allows the

33784 to reset itself if the connection to the Master IC is lost,

or if power is removed from the system, or if a short-to-analog

ground condition exists on one of the bus pins and the bus

switch is closed.

CONTROL LOGIC

The control logic performs the digital operations carried

out by this device. Its principle functions include:

• Decoding input instructions

• Controlling the general purpose I/O in response to

BUSIN commands

• Controlling A/D conversions

• Forming response words

• Capturing and storing addresses

• Controlling the bus switch (BS)

• Resetting the device on power-up

• Reading the general purpose I/O logic values and

responding to requests for these values

• Generating a cycle redundancy check (CRC) for the

received data and transmitted data in conformance with

the DBUS standard

Additionally, the control logic performs error checking on

the received data. If errors are found, no action is taken and

no response is made. Errors include:

• CRC received doesn’t match CRC of received data

• Number of received bits doesn’t match required bit

count

See Figure 6 for the Control Logic Block Diagram

CLOCK

An internal 10 MHz oscillator provides the clock for all logic

and timing functions in the IC. The signaling system and all

internal operations are such that no external precision timing

device is needed in the normal operation of the 33784.

An LFSR-based PRBS is clocked by the oscillator and

generates a random bitstream that dithers the oscillator via a

switch. Dither on the clock creates a spread spectrum for

noise improvement.

ANALOG-TO-DIGITAL CONVERTER

The ADC has 10-bit resolution. It uses REGOUT as a full-

scale reference voltage and AGND for a zero-level reference.

The ADC uses the on-chip oscillator for sequencing.

The analog voltage on AN0 or AN1 is converted to a digital

value in response to the Request AN0 or Request AN1

commands on the bus. Only the Request ANn commands will

trigger a new conversion. The requested bits will be

transmitted during the next command sent on the bus.

To prevent inaccurate reporting near analog ground and

the supply rail, the ADC will only report digital values between

hex 0020 and 03E3. Any analog voltage that would result in

a digital value below 0020 will be reported as 0020. Likewise,

any voltage that would result in a value above 03E3 will be

reported as 03E3. The only time the ADC will report a value

outside the range of hex 0020:03E3 is when an error occurs

during the analog conversion inside the IC. In this case, the

error code 03F8 will be reported. This is summarized in

Table 5, page 14.

The ADC is also designed to report an error depending on

the state of I/O1. If I/O1 is configured as an input and is set

high when the conversion takes place, then the ADC will

always report the error code 03F8. If I/O1 is low when the

conversion takes place, then the ADC will report the

converted digital value as described above. If I/O1 is

configured as an output, then the state of I/O1 is irrelevant

and the ADC will always report the converted digital value, as

described above.

POWER STAGE

TRANSMITTER

At the same moment the receiver detects incoming

commands by sensing the voltage on the bus, the transmitter

replies by changing the current flowing in the bus. Each time

the bus voltage falls below the signal threshold to start a new

incoming bit, the transmitter switches a fixed current source

on or off. A logic [1] is indicated if the current source is

switched on during the bit time. A logic [0] is indicated if the

current source is switched off during the bit time.

The current source is always switched off while the bus is

idle.

As the response current is switched on and off, the

transitions are slew-rate limited to reduce EMI. Without the

slew control, the fast transitions could generate higher

frequency harmonics, that could interfere with receivers

tuned to frequencies well above the data rate of this device.

33784 Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc

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