56F8355 datasheet(79/172 Pages) FREESCALE

79 / 172 page

56F8355 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.1.4

Reserved—Bits 9–0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2

Interrupt Priority Register 1 (IPR1)

Figure 5-4 Interrupt Priority Register 1 (IPR1)

5.6.2.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2.2

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.2.3

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

Base + $1

Read

RX_REG IPL TX_REG IPL

TRBUF IPL

Write

RESET

000000

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