56F8355 datasheet(98/172 Pages) FREESCALE

98 / 172 page

56F8355 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

5.6.16

Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

5.6.16.1

Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAH1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.17

Fast Interrupt 1 Vector Address High Register (FIVAH1)

Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.6.17.1

Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.17.2

Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0

The upper five bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAL1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.18

IRQ Pending 0 Register (IRQP0)

Figure 5-20 IRQ Pending 0 Register (IRQP0)

5.6.18.1

IRQ Pending (PENDING)—Bits 16–2

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2

through 81.

•

0 = IRQ pending for this vector number

•

1 = No IRQ pending for this vector number

Base + $F

Read

FAST INTERRUPT 1

VECTOR ADDRESS LOW

Write

RESET

00000

0000000

0000

Base + $10

Read

FAST INTERRUPT 1

VECTOR ADDRESS HIGH

Write

RESET

00000

0000000

0000

Base + $11

Read

PENDING [16:2]

Write

RESET

11111

1111111

1111

56F8355 Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

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