56F8355 datasheet(19/172 Pages) FREESCALE

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Signal Pins

56F8355 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

2.2 Signal Pins

After reset, all pins are by default the primary function. Any alternate functionality must be programmed.

EMI is not functional in this package; since only part of the address/data bus is bonded out, use as GPIO

pins.

Note: Signals in italics are NOT available in the 56F8155 device.

If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other

states show the reset condition of the alternate function, which you get if the alternate pin function is

selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin

shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the

pin, it will become an input if no other registers are changed.

Table 2-2 Signal and Package Information for the 128-Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

VDD_IO

Supply

I/O Power

— This pin supplies 3.3V power to the chip I/O

interface and also the Processor core throught the on-chip voltage

regulator, if it is enabled.

VDD_IO

112

VDDA_ADC

Supply

ADC Power

— This pin supplies 3.3V power to the ADC modules.

It must be connected to a clean analog power supply.

VDDA_OSC_PLL

Supply

Oscillator

and PLL Power — This pin supplies 3.3V power to the

OSC and to the internal regulator that in turn supplies the Phase

Locked Loop. It must be connected to a clean analog power

supply.

VSS

Supply

VSS — These pins provide ground for chip logic and I/O drivers.

VSS

56F8355 Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc

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