56F8366 datasheet(129/182 Pages) FREESCALE

129 / 182 page

56F8366 Technical Data, Rev. 7

Freescale Semiconductor

129

Preliminary

6.5.9.6

Decoder 0 Enable (DEC0)—Bit 10

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.7

Quad Timer D Enable (TMRD)—Bit 9

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.8

Quad Timer C Enable (TMRC)—Bit 8

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.9

Quad Timer B Enable (TMRB)—Bit 7

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

56F8366 Datasheet(PDF) 129 Page - Freescale Semiconductor, Inc

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