56F8366 datasheet(131/182 Pages) FREESCALE

131 / 182 page

56F8366 Technical Data, Rev. 7

Freescale Semiconductor

131

Preliminary

With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral

registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register

to its previous contents prior to returning from interrupt.

Note:

The default value of this register set points to the EOnCE registers.

Note:

The pipeline delay between setting this register set and using short I/O addressing with the new value

is three cycles.

Figure 6-15 I/O Short Address Location High Register (SIM_ISALH)

6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)

6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.5.11 Peripheral Clock Enable Register 2 (SIM_PCE2)

The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a

power-saving feaure. The clocks can be individually controller for each peripheral on the chip.

6.5.11.1 Reserved—Bits 15–1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $D

Read

ISAL[23:22]

Write

RESET

11111

Base + $E

Read

ISAL[21:6]

Write

RESET

11111

Base + $D

Read

CAN

Write

RESET

00000

56F8366 Datasheet(PDF) 131 Page - Freescale Semiconductor, Inc