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56F8366 Datasheet(PDF) 169 Page - Freescale Semiconductor, Inc |
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56F8366 Datasheet(HTML) 169 Page - Freescale Semiconductor, Inc |
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169 / 182 page ![]() Power Consumption 56F8366 Technical Data, Rev. 7 Freescale Semiconductor 169 Preliminary switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about VREFH - VREFH / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF and the ADC clock frequency. 1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf 3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms 4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1pf Figure 10-24 Equivalent Circuit for A/D Loading 10.18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage current, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static] 1 2 3 Analog Input 4 S1 S2 S3 C1 C2 S/H C1 = C2 = 1pF (VREFH - VREFLO) / 2 |
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