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56F8366 Datasheet(PDF) 165 Page - Freescale Semiconductor, Inc |
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56F8366 Datasheet(HTML) 165 Page - Freescale Semiconductor, Inc |
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165 / 182 page ![]() JTAG Timing 56F8366 Technical Data, Rev. 7 Freescale Semiconductor 165 Preliminary Figure 10-20 Test Clock Input Timing Diagram Figure 10-21 Test Access Port Timing Diagram TCK low to TDO data valid tDV —30 ns 10-21 TCK low to TDO tri-state tTS —30 ns 10-21 TRST assertion time tTRST 2T2 —ns 10-22 1. TCK frequency of operation must be less than 1/8 the processor rate. 2. T = processor clock period (nominally 1/60MHz) Table 10-23 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK (Input) VM VIL VM = VIL + (VIH – VIL)/2 tPW 1/fOP tPW VM VIH Input Data Valid Output Data Valid Output Data Valid tDS tDH tDV tTS tDV TCK (Input) TDI (Input) TDO (Output) TDO (Output) TDO (Output) TMS |
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