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SY54020R Datasheet(PDF) 6 Page - Micrel Semiconductor

Part # SY54020R
Description  Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps, 2.5GHz
PDF  14 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY54020R Datasheet(HTML) 6 Page - Micrel Semiconductor

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Micrel, Inc.
SY54020R
April 2009
6
M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCCO = 1.14V to 1.26V, RL = 50Ω to VCCO
VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50Ω to VCCO or 100Ω across the outputs.
VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
fMAX
Maximum Data Rate/ Frequency
VOUT > 200mV
clock
2.5
GHz
tPD
Propagation Delay
IN-to-Q
VIN > 200mV Note 6, Fig. 1a
VIN: 100mV -200mV, Note 6, Fig. 1a
200
240
300
360
400
490
ps
tS
Setup Time
/EN
150
ps
tH
Hold Time
/EN
250
ps
Output-to-Output skew
Note 7
5
20
ps
tSKEW
Part-to-Part Skew
Note 8
75
ps
Data
Random Jitter
Note 9
1
psRMS
Deterministic Jitter
Note 10
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 11
1
psRMS
tJitter
Total Jitter
Note 12
10
psPP
tR, tF
Output Rise/Fall Times
(20% to 80%)
Input <300mV
35
60
100
ps
Duty Cycle
Differential I/O
≤2.5GHz
47
53
%
Notes:
6.
Propagation delay is measured with input tr/tf
≤ 300ps (20 to 80%)
7.
Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and
transition.
8.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges of the
respective inputs.
9.
Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.



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