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ICS9UMS9633B Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS9UMS9633B Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 22 page ![]() IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device 1423—01/20/09 ICS9UMS9633B ULTRA MOBILE PC/MOBILE INTERNET DEVICE 10 Advance Information Electrical Characteristics - SMBus Interface PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes SMBus Voltage V DD 2.7 3.3 V 1 Low-level Output Voltage V OLSMB @ I PULLUP 0.4 V 1 Current sinking at V OLSMB = 0.4 V I PULLUP SMB Data Pin 4 mA 1 SCLK/SDATA Clock/Data Rise Time T RI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Clock/Data Fall Time T FI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 Maximum SMBus Operating Frequency F SMBUS Block Mode 100 kHz 1 Notes on Electrical Characteristics: 1Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz 7 Operation under these conditions is neither implied, nor guaranteed. 9 See PCI Clock-to-Clock Delay Figure 8 Maximum input voltage is not to exceed maximum VDD 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Clock Periods Differential Outputs with Spread Spectrum Enabled 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+ Absolute Period Short-term Average Long-Term Average Period Long-Term Average Short-term Average Period Minimum Absolute Period Minimum Absolute Period Minimum Absolute Period Nominal Maximum Maximum Maximum SRC 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2 CPU 100 9.91400 9.99900 9.99900 10.00000 10.00100 10.05130 10.13630 ns 1,2 CPU 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2 CPU 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2 Clock Periods Differential Outputs with Spread Spectrum Disabled 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+ Absolute Period Short-term Average Long-Term Average Period Long-Term Average Short-term Average Period Minimum Absolute Period Minimum Absolute Period Minimum Absolute Period Nominal Maximum Maximum Maximum SRC 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2 CPU 100 9.91400 9.99900 10.00000 10.00100 10.13630 ns 1,2 CPU 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2 CPU 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2 DOT 96 10.16560 10.41560 10.41670 10.41770 10.66770 ns 1,2 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Measurement Window Units Notes Symbol Definition Notes Symbol Definition Measurement Window Units |
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