EM68932DVKB datasheet(12/40 Pages) ETRON

12 / 40 page

EtronTech

EM68932DVKB

Etron Confidential

Rev. 1.0

Aug. 2009

DM Masking Function

The DDR SDRAM has a Data Mask function that can be used in conjunction with the data write cycle only,

not the read cycle. When the Data Mask is activated (DM High) during a write operation, the write data is

masked immediately (DM to Data Mask latency is zero). DM must be issued at the rising edge or the falling

edge of Data Strobe instead of at a clock edge.

Auto Precharge Operation

Auto Precharge is a feature which performs the same individual bank precharge function as described

above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to

enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank /

row that is addressed with the READ or WRITE command is automatically performed upon completion of

the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each

individual READ or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest

valid stage within a burst. The user must not issue another command to the same bank until the

precharging time (tRP) is completed. When the Auto Precharge command is activated, the active bank

automatically begins to precharge at the earliest possible moment during a read or write cycle after tRAS

(min) is satisfied.

Precharge Command

The Precharge command is issued when CS , RAS , and WE are Low and CAS is High at the rising edge

of the clock (CK). The Precharge command can be used to precharge any bank individually or all banks

simultaneously. The Bank Select addresses (BA0, BA1) are used to define which bank is precharged when

the command is initiated. For a write cycle, tWR (min) must be satisfied from the start of the last Burst Write

cycle until the Precharge command can be issued. After tRP from the precharge, an Active command to the

same bank can be initiated.

Auto Refresh

An Auto Refresh command is issued by having CS , RAS , and CAS held Low with CKE and WE High at

the rising edge of the clock (CK). All banks must be precharged and idle for a tRP (min) before the Auto

Refresh command is applied. The refresh addressing is generated by the internal refresh address counter.

This makes the address bits “Don’t Care＂ during an Auto Refresh command. When the refresh cycle is

complete, all banks will be in the idle state. A delay between the Auto Refresh command and the next

Active command or subsequent Auto Refresh command must be greater than or equal to the tRFC (min).

Self Refresh

A Self Refresh command is defined by having CS , RAS , CAS and CKE Low with WE High at the rising

edge of the clock (CK). Once the Self Refresh command has been initiated, CKE must be held Low to keep

the device in Self Refresh mode. During the Self Refresh operation, all inputs except CKE are ignored. The

clock is internally disabled during Self Refresh operation to reduce power consumption. To exit the Self

Refresh mode, supply a stable clock input before returning CKE high, assert Deselect or a NOP command,

and then assert CKE high.

Power Down Mode

The device enters Power Down mode when CKE is brought Low, and it exits when CKE returns High. Once

the Power Down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce

power consumption. All banks should be in an idle state prior to entering the Precharge Power Down mode

and CKE should be set high at least tXP prior to an Active command. During Power Down mode, refresh

operations cannot be performed; therefore the device must remain in Power Down mode for a shorter time

than the refresh period (tREF) of the device.

EM68932DVKB Datasheet(PDF) 12 Page - Etron Technology, Inc.

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