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EM68932DVKB Datasheet(PDF) 15 Page - Etron Technology, Inc.

Part # EM68932DVKB
Description  4M x 32 Mobile DDR Synchronous DRAM (SDRAM)
PDF  40 Pages
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM68932DVKB Datasheet(HTML) 15 Page - Etron Technology, Inc.

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EtronTech
EM68932DVKB
Etron Confidential
15
Rev. 1.0
Aug. 2009
Table 11. D.C. Characteristics (VDD=1.7V~1.95V, TA =-25~85°C)
-6
-75
Parameter & Test Condition
Symbol
Max.
Unit
Operating one bank active-precharge current:
tRC=tRC(min); tCK=tCK(min); CKE is HIGH; CS is HIGH between valid
commands; Address inputs are SWITCHING; data bus inputs are STABLE
IDD0
45
40
mA
Precharge power-down standby current:
All banks idle, CKE is LOW; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2P
0.1
0.1
mA
Precharge power-down standby current with clock stop:
All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2PS
0.1
0.1
mA
Precharge non power-down standby current:
All banks idle, CKE is HIGH; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2N
15
15
mA
Precharge non power-down standby current with clock stop:
All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD2NS
8
8
mA
Active power-down standby current:
One bank active, CKE is LOW; CS is HIGH, tCK=tCK(min);
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3P
3
3
mA
Active power-down standby current with clock stop:
One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS
2
2
mA
Active non power-down standby current:
One bank active, CKE is HIGH; CS is HIGH, tCK=tCK(min) address and
control inputs are SWITCHING; data bus inputs are STABLE
IDD3N
20
20
mA
Active non power-down standby current with clock stop:
One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3NS
10
10
mA
Operating burst read current:
One bank active; BL = 4; CL = 3; tCK=tCK(min); continuous read bursts; IOUT =
0 mA address inputs are SWITCHING; 50% data change each burst transfer
IDD4R
150
130
mA
Operating burst write current:
One bank active; BL = 4; tCK=tCK(min); continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
IDD4W
150
130
mA
Auto-Refresh current:
tRFC = tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD5
70
70
mA
TCSR Range
Max. 40
Max.85
℃
Full Array
160
200
µA
1/2 Full Array
110
150
µA
Self refresh current:
CKE is LOW, CK = LOW, CK = HIGH; Extended Mode
Register set to all address and control inputs are STABLE;
data bus inputs are STABLE
1/4 Full Array
IDD6
90
120
µA
Deep Power Down Mode Current
IDD8
10
µA
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time per two clock cycles.



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