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EM68932DVKB Datasheet(PDF) 16 Page - Etron Technology, Inc.

Part # EM68932DVKB
Description  4M x 32 Mobile DDR Synchronous DRAM (SDRAM)
PDF  40 Pages
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM68932DVKB Datasheet(HTML) 16 Page - Etron Technology, Inc.

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EtronTech
EM68932DVKB
Etron Confidential
16
Rev. 1.0
Aug. 2009
Table 12. Electrical AC Characteristics (VDD=1.7V~1.95V, TA =-25~85°C)
-6
-75
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit Note
CL = 2
12
-
12
-
ns
1
tCK
Clock cycle time
CL = 3
6
100
7.5
100
ns
1
tCH
Clock high level width
0.45
0.55
0.45
0.55
tCK
tCL
Clock low level width
0.45
0.55
0.45
0.55
tCK
tDQSCK
DQS-out access time from CK, CK
2
5.5
2
6
ns
tAC
Output access time from CK, CK
2
5.5
2
6
ns
2
tDQSQ
DQS-DQ Skew
-
0.5
-
0.6
ns
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK
tDQSS
CK to valid DQS-in
0.75
1.25
0.75
1.25
tCK
tWPRES
DQS-in setup time
0
-
0
-
ns
3
tWPRE
DQS write preamble
0.25
-
0.25
-
tCK
tWPST
DQS write postamble
0.4
0.6
0.4
0.6
tCK
tDQSH
DQS in high level pulse width
0.4
0.6
0.4
0.6
tCK
tDQSL
DQS in low level pulse width
0.4
0.6
0.4
0.6
tCK
tIS
Address and Control input setup time
1.1
-
1.3
-
ns
1
tIH
Address and Control input hold time
1.1
-
1.3
-
ns
1
tDS
DQ & DM setup time to DQS
0.6
-
0.8
-
ns
4, 5
tDH
DQ & DM hold time to DQS
0.6
-
0.8
-
ns
4, 5
tHP
Clock half period
tCLMIN or
tCHMIN
-
tCLMIN or
tCHMIN
-
ns
tQH
Output DQS valid window
tHP –
0.65
-
tHP –
0.75
-
ns
tRC
Row cycle time
60
-
67.5
-
ns
tRFC
Refresh row cycle time
110
-
110
-
ns
tRAS
Row active time
42
100K
45
100K
ns
tRCD
ACTIVE to READ or WRITE delay
18
-
22.5
-
ns
tRP
Row precharge time
18
-
22.5
-
ns
tRRD
Row active to Row active delay
12
-
15
-
ns
twR
Write recovery time
12
-
15
-
ns
8
tDAL
Auto precharge write recovery + Precharge time
tWR+tRP
-
tWR+tRP
-
tCK
tWTR
Internal Write to Read Delay
2
-
1
-
tCK
7
tCCD
Col. Address to Col. Address delay
1
-
1
-
tCK
tMRD
Mode register set cycle time
2
-
2
-
tCK
tXSR
Self refresh exit to next valid command delay
200
-
200
-
ns
tXP
Exit Power Down mode to first valid command
25
-
25
-
ns
6
tREFI
Refresh interval time
-
15.6
-
15.6
µs
Note:
1. Table 13.Input Setup / Hold Slew Rate Derating
Input Setup/Hold Slew Rate (V/ns)
△
tIS (ps)
△
tIH (ps)
1.0
0
0
0.8
+50
+50
0.6
+100
+100
This derating table is used to increase tIS / tIH in the case where the input slew rate is below 1.0V/ns.



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