AT89LP6440 datasheet(133/194 Pages) ATMEL

133 / 194 page

133

3706A–MICRO–9/09

AT89LP6440 - Preliminary

20. Digital-to-Analog/Analog-to-Digital Converter

The AT89LP6440 includes a 10-bit Data Converter (DADC) with the following features:

• Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode

•10-bit Resolution

• 6.5 µs Conversion Time

• 8 Multiplexed Single-ended Channels or 4 Differential Channels

• Selectable 1.0V±10% Internal Reference Voltage

•Optional Left-Adjust of Conversion Results

• Single Conversion or Timer-triggered Mode

• Interrupt on Conversion Complete

The AT89LP6440 features a 10-bit successive approximation data converter that functions in

either Analog-to-Digital (ADC) or Digital-to-Analog (DAC) mode. A block diagram of the con-

verter is shown in Figure 20-1. An 8-channel Analog Multiplexer connects eight single-ended or

four differential voltage inputs from the pins of Port 0 to a sample-and-hold circuit that in turn

provides an input to the successive approximation block. The Sample-and-Hold circuit ensures

that the input voltage to the ADC is held at a constant level during conversion. The SAR block

digitizes the analog voltage into a 10-bit value accessible through a data register. The SAR

block also operates in reverse to generate an analog voltage on Port 2 from a 10-bit digital

value. The DADC has separate analog supply pins, AVDD and AGND, which must not differ more

than ± 0.3V from the standard supplies VDD and GND.

ADC results are available in the DADL and DADH register pair. The ADC result scale is deter-

mined by the reference voltage (VREF) generated either internally from a 1.0V reference or

externally from AVDD/2. The ADC results are always represented in signed 2’s complement

form, with single-ended voltage channels referring to the level above or below AVDD/2. The 10-

bit results may be right or left adjusted within the 16-bit register. The sign is extended through

the 6 MSBs of right-adjusted results and the 6 LSBs of left-adjusted results are zeroed. If only 8-

bit precision is required, the user should select left-adjusted by setting LADJ in DADC and read

only the DADH register. Example results are listed in Table 20-1.

The conversion formulas are as follows:

Conversion results can be converted into unsigned binary by adding 02h to DADH in right-

adjusted mode or 80h to DADH in left-adjusted mode. When using the external reference

(AVDD/2) in single-ended mode this is equivalent to:

To convert the unsigned binary value back to 2’s complement, subtract 02h from DADH in right-

adjusted mode or 80h from DADH in left-adjusted mode. Note that the DADH/DADL registers

cannot be directly manipulated as they are read-only in ADC mode and write-only in DAC mode.

(Singled-Ended)

ADC

511

⁄

REF

(Differential)

ADC

511

IN+

IN-

REF

(Unsigned Singled-Ended)

ADC

1023

AT89LP6440 Datasheet(PDF) 133 Page - ATMEL Corporation

AT89LP6440 Datasheet(HTML) 133 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL