AT89LP6440 datasheet(137/194 Pages) ATMEL

137 / 194 page

137

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 20-5. Equivalent Analog Output Model

20.3

Clock Selection

The DADC requires a clock of 2 MHz or less to achieve full resolution. By default the DADC will

use an internal 2 MHz clock generated from the 8 MHz internal oscillator. The internal oscillator

will be enabled even if it is not supplying the system clock. This may result in higher power con-

sumption. Conversely, the DADC clock can be generated directly from the system clock using a

7-bit prescaler. The prescaler output is controlled by the ACK bits in DADC as shown in Figure

20-6.

In ADC mode, there are no requirements on the clock frequency with respect to the system

clock. The ADC prescaler selection is independent of the system clock divider and the ADC may

operate at both higher or lower frequencies than the CPU. However, in DAC mode the ADC

clock frequency must not be higher than the CPU clock, including any clock division from the

system clock.

Figure 20-6. DADC Clock Selection

20.4

Starting a Conversion

Setting the GO/BSY bit (DADC.6) when ADCE = 1 starts a single conversion in both ADC and

DAC modes. The bit remains set while the conversion is in progress and is cleared by hardware

when the conversion completes. The ADC channel should not be changed while a conversion is

in progress.

Alternatively, a conversion can be started automatically by various timer sources. Conversion

trigger sources are selected by the TRG bits in DADI. A conversion is started every time the

selected timer overflows, allowing for conversions to occur at fixed intervals. The GO/BSY bit will

DAn

VOUT

ROUT =

100 k

CPIN =

10 pF

AVDD/2

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ACK0

ACK1

ACK2

INTERNAL

8MHz OSC

÷ 4

AT89LP6440 Datasheet(PDF) 137 Page - ATMEL Corporation

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