AT89LP6440 datasheet(136/194 Pages) ATMEL

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3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 20-3. Equivalent Analog Input Model

20.2

DAC Operation

The DAC converts a 10-bit signed digital value to an analog output voltage through successive

approximation. The DAC always operates in differential mode, outputting a voltage differential

between its positive (P2.2) and negative (P2.3) outputs with a common mode of AVDD/2. The

minimum value represents zero difference and the maximum values represent a difference of

positive or negative VREF minus 1 LSB.

The DAC is enabled by setting the ADCE and DAC bits in DADC. Some settling time is required

for the reference circuits to stabilize after the DAC is enabled. The DAC does not have multiple

output channels and the DIFF, ACON and ACS bits have no effect in DAC mode. P2.2 and P2.3

are automatically forced to input-only mode while the DAC is enabled.

A timing diagram of a DAC conversion is shown in Figure 20-4. The conversion requires 11 ADC

clock cycles to complete. Construction of the analog output starts in the second cycle of the con-

version and the DAC will allow the new value to propagate to the outputs during cycle 7, after the

5 MSBs are complete. At the end of the conversion, the interrupt flag is set. An additional 1 ADC

clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of

the system. The DADL and DADH registers hold the value to be output and are write-only during

DAC mode. An internal buffer samples DADH/DADL at the start of the conversion and holds the

value constant for the remainder of the conversion. One system clock cycle is required to trans-

fer the contents of DADH/DADL into the buffer at the start of the conversion and therefore the

ADC clock frequency must always be equal to or less than the system clock frequency during

DAC mode to ensure that the buffer is updated before the second cycle.

Figure 20-4. DAC Timing Diagram

The equivalent model for the analog output circuitry is illustrated in Figure 20-5. The series out-

put resistance of the DAC must drive the pin capacitance and any external load on the pin.

ADCn

CS/H =

2 pF

RIN =

10 k

CPIN =

10 pF

RMUX =

10 k

456789

MSB of Output

LSB of Output

ADC Clock

GO/BSY

ADIF

DADH

DADL

Cycle Number

One Conversion

Next Conversion

Begin Output

Initialize Circuitry

Conversion

Complete

Initialize

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