AT89LP6440 datasheet(135/194 Pages) ATMEL

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135

3706A–MICRO–9/09

AT89LP6440 - Preliminary

20.1

ADC Operation

The ADC converts an analog input voltage to a 10-bit signed digital value through successive

approximation. When DIFF (DADI.3) is zero, the ADC operates in single-ended mode and the

input voltage is the difference between the voltage at the input pin and AVDD/2. In differential

mode (DIFF = 1) the input voltage is the difference between the positive and negative input pins.

The minimum value represents zero difference and the maximum values represent a difference

of positive or negative VREF minus 1 LSB.

The analog input channel is selected by writing to the ACS bits in DADI. Any of the eight Port 0

input pins can be selected as single-ended inputs to the ADC. Four pairs of Port 0 pins can be

selected as differential inputs. The ACON bit (DADI.7) must be set to one to connect the input

pins to the ADC. Prior to changing ACS, ACON must be cleared to zero. This ensures that

crosstalk between channels is limited. ACON must be set back to one after ACS is updated.

ACON and ACS should not be changed while a conversion is in progress. ADC input channels

must have their port pins configured for input-only mode.

The ADC is enabled by setting the ADCE bit in DADC. Some settling time is required for the ref-

erence circuits to stabilize after the ADC is enabled. The ADC does not consume power when

ADCE is cleared, so it is recommended to switch off the ADC before entering power saving

modes.

A timing diagram of an ADC conversion is shown in Figure 20-2. The conversion requires 13

ADC clock cycles to complete. The analog input is sampled during the third cycle of the conver-

sion and is held constant for the remainder of the conversion. At the end of the conversion, the

interrupt flag, ADIF, is set and the result is written to the data registers. An additional 1 ADC

clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of

the system. The results in DADH/DADL remain valid until the next conversion completes. DADH

and DADL are read-only registers during ADC mode.

Figure 20-2. ADC Timing Diagram

The equivalent model for the analog input circuitry is illustrated in Figure 20-3. An analog source

applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of

whether that channel is selected as input to the ADC. When the channel is selected, the source

must drive the S/H capacitor through the series resistance (combined resistance in the input

path). To achieve 10-bit resolution the S/H capacitor must be charged to within 1/2 LSB of the

expected value within the 1 ADC clock period sample time. High impedance sources may

require a reduction in the ADC clock frequency to achieve full resolution.

10111213

MSB of Result

LSB of Result

ADC Clock

GO/BSY

ADIF

DADH

DADL

Cycle Number

One Conversion

Next Conversion

Sample & Hold

Initialize Circuitry

Conversion

Complete

Initialize

AT89LP6440 Datasheet(PDF) 135 Page - ATMEL Corporation

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