AT91SAM9263 datasheet(63/1110 Pages) ATMEL

63 / 1110 page

6249H–ATARM–27-Jul-09

AT91SAM9263 Preliminary

11.7.2

Enabling and Disabling TCMs

Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register.

Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user

should use the same sizes as those put in HMATRIX TCM register. For further details and pro-

gramming tips, please refer to chapter 2.3 in ARM926EJ-S TRM, ref. DDI0222B.

11.7.3

TCM Mapping

The TCMs can be located anywhere in the memory map, with a single region available for ITCM

and a separate region available for DTCM. The TCMs are physically addressed and can be

placed anywhere in physical address space. However, the base address of a TCM must be

aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is per-

formed by using TCM region register (register 9) in CP15. The user should input the right

mapping address for TCMs.

11.8

Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB

requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables

parallel access paths between multiple AHB masters and slaves in a system. This is achieved by

using a more complex interconnection matrix and gives the benefit of increased overall bus

bandwidth, and a more flexible system architecture.

The multi-master bus architecture has a number of benefits:

• It allows the development of multi-master systems with an increased bus bandwidth and a

flexible architecture.

• Each AHB layer becomes simple because it only has one master, so no arbitration or master-

to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to

support request and grant, nor do they have to support retry and split transactions.

• The arbitration becomes effective when more than one master wants to access the same

slave simultaneously.

11.8.1

Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or

bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into

packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not

support split and retry requests.

Table 11-7 gives an overview of the supported transfers and different kinds of transactions they

are used for.

AT91SAM9263 Datasheet(PDF) 63 Page - ATMEL Corporation