ATmega324P datasheet(14/377 Pages) ATMEL

14 / 377 page

7674F–AVR–09/09

ATmega164P/324P/644P

5.5.1

SPH and SPL – Stack Pointer High and Stack pointer Low

5.6

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 5-4 on page 14 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions

per cost, functions per clocks, and functions per power-unit.

Figure 5-4.

The Parallel Instruction Fetches and Instruction Executions

Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Bit

151413121110

0x3E (0x5E)

–

SP12

SP11

SP10

SP9

SP8

SPH

0x3D (0x5D)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

765

432

Read/Write

R/W

Initial Value

111

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

ATmega324P Datasheet(PDF) 14 Page - ATMEL Corporation

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