ATmega324P datasheet(153/377 Pages) ATMEL

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153

7674F–AVR–09/09

ATmega164P/324P/644P

15.10 Timer/Counter Prescaler

Figure 15-12. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clk

T2S. clkT2S is by default connected to the main

system I/O clock clk

IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. By set-

ting the EXCLK bit in the ASSR a 32 kHz external clock can be applied. See “ASSR –

Asynchronous Status Register” on page 158 for details.

For Timer/Counter2, the possible prescaled selections are: clk

T2S/8, clkT2S/32, clkT2S/64,

clk

T2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

15.11 Register Description

15.11.1

TCCR2A – Timer/Counter Control Register A

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clk

I/O

clk

T2S

TOSC1

AS2

CS20

CS21

CS22

PSRASY

Clear

clk

Bit

210

(0xB0)

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

TCCR2A

Read/Write

R/W

Initial Value

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