ATmega324P datasheet(194/377 Pages) ATMEL

194 / 377 page

194

7674F–AVR–09/09

ATmega164P/324P/644P

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

17.11.5

UBRRnL and UBRRnH – USART Baud Rate Registers

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four

most significant bits, and the UBRRL contains the eight least significant bits of the USART baud

rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is

changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.

101

Reserved

110

Reserved

111

9-bit

Table 17-8.

UCPOLn Bit Settings

UCPOLn

Transmitted Data Changed (Output of

TxDn Pin)

Received Data Sampled (Input on RxDn

Pin)

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

Table 17-7.

UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

Bit

13121110

––––

UBRR[11:8]

UBRRHn

UBRR[7:0]

UBRRLn

76543210

Read/Write

RRRR

R/W

Initial Value

00000000

ATmega324P Datasheet(PDF) 194 Page - ATMEL Corporation

ATmega324P Datasheet(HTML) 194 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL