ATmega324P datasheet(312/377 Pages) ATMEL

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312

7674F–AVR–09/09

ATmega164P/324P/644P

25.8.2

Serial Programming Algorithm

When writing serial data to the ATmega164P/324P/644P, data is clocked on the rising edge of

SCK.

When reading data from the ATmega164P/324P/644P, data is clocked on the falling edge of

SCK. See Figure 25-12 for timing details.

To program and verify the ATmega164P/324P/644P in the serial programming mode, the follow-

ing sequence is recommended (See four byte instruction formats in Table 25-17

Power-up sequence:

Apply power between V

CC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

The Flash is programmed one page at a time. The memory page is loaded one byte at a

time by supplying the 7 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the address

lines 15..8. Before issuing this command, make sure the instruction Load Extended

Address Byte has been used to define the MSB of the address. The extended address

byte is stored until the command is re-issued, i.e., the command needs only be issued for

the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not

used, the user must wait at least t

WD_FLASH before issuing the next page. (See Table

25-16.) Accessing the serial programming interface before the Flash write operation

completes can result in incorrect programming.

The EEPROM array is programmed one byte at a time by supplying the address and data

together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling is not used, the user must wait

at least t

WD_EEPROM before issuing the next byte. (See Table 25-16.) In a chip erased

device, no 0xFFs in the data file(s) need to be programmed.

Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO. When reading the Flash memory, use

the instruction Load Extended Address Byte to define the upper address byte, which is

not included in the Read Program Memory instruction. The extended address byte is

stored until the command is re-issued, i.e., the command needs only be issued for the

first page, and when crossing the 64KWord boundary.

At the end of the programming session, RESET can be set high to commence normal

operation.

Power-off sequence (if needed):

Set RESET to “1”.

Turn V

CC power off.

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