ATmega88 datasheet(83/340 Pages) ATMEL

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7530H–AVR–02/09

ATmega48/88/168 Automotive

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT0 is configured as an output. The corresponding interrupt of External

Interrupt Request 0 is executed from the INT0 Interrupt Vector.

11.0.3

External Interrupt Flag Register – EIFR

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set

(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

11.0.4

Pin Change Interrupt Control Register - PCICR

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 - PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2

Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

Bit

6543

210

–

––––

–

INTF1

INTF0

EIFR

Read/Write

RRRR

R/W

Initial Value

0000

000

Bit

6543

210

–

––––

PCIE2

PCIE1

PCIE0

PCICR

Read/Write

RRRR

R/W

Initial Value

0000

000

ATmega88 Datasheet(PDF) 83 Page - ATMEL Corporation

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