ATmega88 datasheet(47/340 Pages) ATMEL

47 / 340 page

7530H–AVR–02/09

ATmega48/88/168 Automotive

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

Note:

1. Values are guidelines only. Actual values are TBD.

8.2

Watchdog Timer

ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The main features are:

• Clocked from separate On-chip Oscillator

• 3 Operating modes

–Interrupt

– System Reset

– Interrupt and System Reset

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 8-7.

Watchdog Timer

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.

The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.

In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset

- instruction to restart the counter before the time-out value is reached. If the system doesn't

restart the counter, an interrupt or system reset will be issued.

Table 8-4.

Internal Voltage Reference Characteristics

(1)

Symbol

Parameter

Condition

Min

Typ

Max

Units

VBG

Bandgap reference voltage

TBD

1.0

1.1

1.2

tBG

Bandgap reference start-up time

TBD

µs

IBG

Bandgap reference current consumption

TBD

µA

128kHz

OSCILLATOR

WDP0

WDP1

WDP2

WDP3

WATCHDOG

RESET

WDE

WDIF

WDIE

MCU RESET

INTERRUPT

ATmega88 Datasheet(PDF) 47 Page - ATMEL Corporation

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