ATmega88 datasheet(166/340 Pages) ATMEL

166 / 340 page

166

7530H–AVR–02/09

ATmega48/88/168 Automotive

Figure 17-1. USART Block Diagram(1)

Note:

1. Refer to Figure 1-1 on page 2 and Table 10-9 on page 77 for USART0 pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

PARITY

GENERATOR

UBRRn [H:L]

UDRn(Transmit)

UCSRnA

UCSRnB

UCSRnC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxDn

TxDn

CONTROL

UDRn(Receive)

CONTROL

XCKn

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

ATmega88 Datasheet(PDF) 166 Page - ATMEL Corporation

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