ATmega88 datasheet(251/340 Pages) ATMEL

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7530H–AVR–02/09

ATmega48/88/168 Automotive

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a

Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI

and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

21.6.3

The ADC Data Register – ADCL and ADCH

21.6.3.1

ADLAR = 0

Table 21-4.

ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

128

Bit

14131211

––––––

ADC9

ADC8

ADCH

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

765432

Read/Write

RRRR

Initial Value

000000

ATmega88 Datasheet(PDF) 251 Page - ATMEL Corporation

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