ATmega16U4 datasheet(174/408 Pages) ATMEL

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174

7766D–AVR–01/09

ATmega16U4/ATmega32U4

When the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter4 Compare Match B interrupt is enabled. The corresponding interrupt at vector

$009 is executed if a compare match B occurs. The Compare Flag in Timer/Counter4 is set

(one) in the Timer/Counter Interrupt Flag Register.

• Bit 2 - TOIE4: Timer/Counter4 Overflow Interrupt Enable

When the TOIE4 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter4 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter4 occurs. The Overflow Flag (Timer4) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR4.

15.12.13 TIFR4 – Timer/Counter4 Interrupt Flag Register

• Bit 7- OCF4D: Output Compare Flag 4D

The OCF4D bit is set (one) when compare match occurs between Timer/Counter4 and the data

value in OCR4D - Output Compare Register 4D. OCF4D is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF4D is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE4D, and OCF4D

are set (one), the Timer/Counter4 D compare match interrupt is executed.

• Bit 6 - OCF4A: Output Compare Flag 4A

The OCF4A bit is set (one) when compare match occurs between Timer/Counter4 and the data

value in OCR4A - Output Compare Register 4A. OCF4A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF4A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE4A, and OCF4A

are set (one), the Timer/Counter4 A compare match interrupt is executed.

• Bit 5 - OCF4B: Output Compare Flag 4B

The OCF4B bit is set (one) when compare match occurs between Timer/Counter4 and the data

value in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF4B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE4B, and OCF4B

are set (one), the Timer/Counter4 B compare match interrupt is executed.

• Bit 2 - TOV4: Timer/Counter4 Overflow Flag

In Normal Mode and Fast PWM Mode the TOV4 bit is set (one) each time the counter reaches

TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency

Correct PWM Mode the TOV4 bit is set (one) each time the counter reaches BOTTOM at the

same clock cycle when zero is clocked to the counter.

The bit TOV4 is cleared by hardware when executing the corresponding interrupt handling vec-

tor. Alternatively, TOV4 is cleared, after synchronization clock cycle, by writing a logical one to

the flag. When the SREG I-bit, and TOIE4 (Timer/Counter4 Overflow Interrupt Enable), and

TOV4 are set (one), the Timer/Counter4 Overflow interrupt is executed.

Bit

76543210

OCF4D

OCF4A

OCF4B

TOV4

TIFR4

Read/Write

R/W

Initial value

00000000

ATmega16U4 Datasheet(PDF) 174 Page - ATMEL Corporation

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