ATmega16U4 datasheet(170/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

• Bit 3 - FPAC4: Fault Protection Analog Comparator Enable

When written logic one, this bit enables the Fault Protection function in Timer/Counter4 to be

triggered by the Analog Comparator. The comparator output is in this case directly connected to

the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge

select features of the Timer/Counter4 Fault Protection interrupt. When written logic zero, no con-

nection between the Analog Comparator and the Fault Protection function exists. To make the

comparator trigger the Timer/Counter4 Fault Protection interrupt, the FPIE4 bit in the

Timer/Counter4 Control Register D (TCCR4D) must be set.

• Bit 2- FPF4: Fault Protection Interrupt Flag

When the FPIE4 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will

cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre-

sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection

Interrupt Vector. The bit FPF4 is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, FPF4 is cleared after a synchronization clock cycle by writing

a logical one to the flag. When the SREG I-bit, FPIE4 and FPF4 are set, the Fault Interrupt is

executed.

• Bits 1:0 - WGM41, WGM40: Waveform Generation Mode Bits

This bit associated with the PWM4x bits control the counting sequence of the counter, the

source for type of waveform generation to be used, see Table 15-19. Modes of operation sup-

ported by the Timer/Counter4 are: Normal mode (counter), Fast PWM Mode, Phase and

Frequency Correct PWM and PWM6 Modes.

15.12.5

TCCR4E – Timer/Counter4 Control Register E

• Bit 7 - TLOCK4: Register Update Lock

This bit controls the Compare registers update. When this bit is set, writing to the Compare reg-

isters will not affect the output, however the values are stored and will be updated to the

Compare registers when the TLOCK4 bit will be cleared.

Refer to Section 15.7 ”Synchronous update” on page 150 for more details.

• Bit 6- ENHC4: Enhanced Compare/PWM Mode

Table 15-19. Waveform Generation Mode Bit Description

PWM4x

WGM41..40

Timer/Counter Mode of Operation

TOP

Update of

OCR4x at

TOV4 Flag

Set on

Normal

OCR4C

Immediate

TOP

Fast PWM

OCR4C

TOP

Phase and Frequency Correct PWM

OCR4C

BOTTOM

PWM6 / Single-slope

OCR4C

TOP

PWM6 / Dual-slope

OCR4C

BOTTOM

Bit

76543210

TLOCK4

ENHC4

OC4OE5

OC4OE4

OC4OE3

OC4OE2

OC4OE1

OC4OE0

TCCR4E

Read/Write

R/W

Initial value

00000000

ATmega16U4 Datasheet(PDF) 170 Page - ATMEL Corporation

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