ATmega16M1 datasheet(156/365 Pages) ATMEL

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156

7647F–AVR–04/09

ATmega16/32/64/M1/C1

Table 14-12. Input Mode Operation

14.16.10 PSC Interrupt Mask Register – PIM

• Bit 7:4 – not use

not use.

• Bit 3 – PEVE2 : PSC External Event 2 Interrupt Enable

When this bit is set, an external event which can generates a a fault on module 2 generates also

an interrupt.

• Bit 2 – PEVE1 : PSC External Event 1 Interrupt Enable

When this bit is set, an external event which can generates a fault on module 1 generates also

an interrupt.

• Bit 1 – PEVE0 : PSC External Event 0 Interrupt Enable

When this bit is set, an external event which can generates a fault on module 0 generates also

an interrupt.

• Bit 0 – PEOPE : PSC End Of Cycle Interrupt Enable

When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.

PRFMn2:0

Description

000b

No action, PSC Input is ignored

001b

Disactivate module n Outputs A

010b

Disactivate module n Output B

011b

Disactivate module n Output A & B

10x

Disactivate all PSC Output

11xb

Halt PSC and Wait for Software Action

Bit

654

PEVE2

PEVE1

PEVE0

PEOPE

PIM

Read/Write

R/W

Initial Value

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