ATmega16M1 datasheet(154/365 Pages) ATMEL

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154

7647F–AVR–04/09

ATmega16/32/64/M1/C1

• Bit 4 – PMODE PSC Mode

Select the mode of PSC.

• Bit 3 – POPB: PSC B Output Polarity

If this bit is cleared, the PSC outputs B are active Low.

If this bit is set, the PSC outputs B are active High.

• Bit 2 – POPA: PSC A Output Polarity

If this bit is cleared, the PSC outputs A are active Low.

If this bit is set, the PSC outputs A are active High.

• Bit 1:0 – not use

not use

14.16.8

PSC Control Register – PCTL

• Bit 7:6 – PPRE1:0 : PSC Prescaler Select

This two bits select the PSC input clock division factor. All generated waveform will be modified

by this factor.

• Bit 5 – PCLKSEL: PSC Input Clock Select

This bit is used to select between CLK

PLL or CLKIO clocks.

Set this bit to select the fast clock input (CLK

PLL).

Clear this bit to select the slow clock input (CLK

IO).

Table 14-10. PSC Mode Selection

PMODE

Description

One Ramp Mode (Edge Aligned)

Center Aligned Mode

Bit

654

PPRE1

PPRE0

PCLKSEL

SWAP2

SWAP1

SWAP0

PCCYC

PRUN

PCTL

Read/Write

R/W

Initial Value

Table 14-11. PSC Prescaler Selection

PPRE1

PPRE0

Description

No divider on PSC input clock

Divide the PSC input clock by 4

Divide the PSC input clock by 32

Divide the PSC clock by 256

ATmega16M1 Datasheet(PDF) 154 Page - ATMEL Corporation

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