ATmega3290P datasheet(241/385 Pages) ATMEL

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241

8021E–AVR–07/09

ATmega329P/3290P

• Bit 3 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0

The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are

shown in Table 22-5. This Clock Divider gives extra flexibility in frame rate selection.

The frame frequency can be calculated by the following equation:

Where:

N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).

K = 8 for duty = 1/4, 1/2, and static.

K = 6 for duty = 1/3.

D = Division factor (see Table 22-5 on page 241)

This is a very flexible scheme, and users are encouraged to calculate their own table to investi-

gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate

clkLCD/1024

520 kHz

clk

LCD/2048

1 MHz

clkLCD/4096

2 MHz

Table 22-5.

LCD Clock Divide

LCDCD2

LCDCD1

LCDCD0

Output from

Prescaler

divided by (D) :

clkLCD = 32.768 kHz, N = 16, and Duty =

1/4, gives a frame rate of:

000

256 Hz

001

128 Hz

85.3 Hz

011

64 Hz

51.2 Hz

42.7 Hz

36.6 Hz

111

32 Hz

Table 22-4.

LCD Prescaler Select (Continued)

LCDPS2

LCDPS1

LCDPS0

Output from

Prescaler

clk

LCD/N

Applied Prescaled LCD Clock Frequency

when LCDCD2:0 = 0, Duty = 1/4, and

Frame Rate = 64 Hz

fframe

fclk

LCD

KND

⋅⋅

()

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