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ATmega3290P Datasheet(PDF) 240 Page - ATMEL Corporation |
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ATmega3290P Datasheet(HTML) 240 Page - ATMEL Corporation |
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240 / 385 page ![]() 240 8021E–AVR–07/09 ATmega329P/3290P Note: 1. LCDPM3 is reserved and will always read as zero in ATmega329P/649P. 22.5.3 LCDFRR – LCD Frame Rate Register • Bit 7 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 6:4 – LCDPS2:0: LCD Prescaler Select The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in Table 22-4. Together they determine the prescaled LCD clock (clk LCD_PS), which is clocking the LCD module. 0 1 0 0 SEG0:20 21 0 1 0 1 SEG0:22 23 0 1 1 0 SEG0:23 24 0 1 1 1 SEG0:24 25 1 0 0 0 SEG0:26 27 1 0 0 1 SEG0:28 29 1 0 1 0 SEG0:30 31 1 0 1 1 SEG0:32 33 1 1 0 0 SEG0:34 35 1 1 0 1 SEG0:36 37 1 1 1 0 SEG0:38 39 1 1 1 1 SEG0:39 40 Table 22-3. LCD Port Mask (Values in bold are only available in ATmega3290P) (Continued) LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O Port in Use as Segment Driver Maximum Number of Segments Bit 7 6 5 4 3 210 (0xE6) – LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 LCDFRR Read/Write R R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 22-4. LCD Prescaler Select LCDPS2 LCDPS1 LCDPS0 Output from Prescaler clk LCD/N Applied Prescaled LCD Clock Frequency when LCDCD2:0 = 0, Duty = 1/4, and Frame Rate = 64 Hz 00 0 clk LCD/16 8.1 kHz 00 1 clkLCD/64 33 kHz 01 0 clk LCD/128 66 kHz 01 1 clkLCD/256 130 kHz 10 0 clkLCD/512 260 kHz |
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