ATmega644PA datasheet(300/468 Pages) ATMEL

300 / 468 page

300

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

26.6

Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATmega164PA/324PA/644PA/1284P.

Pulses are assumed to be at least 250 ns unless otherwise noted.

26.6.1

Signal Names

In this section, some pins of the ATmega164PA/324PA/644PA/1284P are referenced by signal

names describing their functionality during parallel programming, see Figure 26-1 on page 300

and Figure 26-9 on page 300. Pins not described in the following table are referenced by pin

names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 26-12 on page 301.

When pulsing WR or OE, the command loaded determines the action executed. The different

commands are shown in Table 26-13 on page 301.

Figure 26-1. Parallel Programming

(1)

Note:

1. Unused Pins should be left floating.

Table 26-9.

Pin Name Mapping

Signal Name in

Programming Mode

Pin Name

I/O

Function

RDY/BSY

PD1

0: Device is busy programming, 1: Device is ready for

new command.

PD2

Output Enable (Active low).

PD3

Write Pulse (Active low).

BS1

PD4

Byte Select 1.

XA0

PD5

XTAL Action Bit 0

XA1

PD6

XTAL Action Bit 1

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0

DATA

RESET

PD7

+12 V

BS1

XA0

XA1

RDY/BSY

PAGEL

PA0

BS2

AVCC

+5V

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