Bypass AVDD and DVDD to the ground plane with

0.1µF ceramic chip capacitors on each pin as close as

possible to the device to minimize parasitic inductance.

Add at least one bulk 10µF decoupling capacitor to

AVDD and DVDD per PCB. Interconnect all of the

AVDD inputs and DVDD inputs using two solid power

planes. For best performance, bring the AVDD power

plane in on the analog interface side of the MAX11044/

MAX11045/MAX11046 and the DVDD power plane from

the digital interface side of the device.

For acquisition periods near minimum (1µs) use a 1nF

C0G ceramic chip capacitor between each of the chan-

nel inputs to the ground plane as close as possible to

the MAX11044/MAX11045/MAX11046. This capacitor

reduces the inductance seen by the sampling circuitry

and reduces the voltage transient seen by the input

source circuit.

Typical Application Circuits

Power-Grid Protection

Figure 10 shows a typical power-grid protection application.

DSP Motor Control

Figure 11 shows a typical DSP motor control application.

Definitions

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer

function from a straight line. For these devices, this

straight line is a line drawn between the end points of

the transfer function, once offset and gain errors have

been nullified.

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and

the ideal value of 1 LSB. For these devices, the DNL of

each digital output code is measured and the worst-case

value is reported in the

Electrical Characteristics table. A

DNL error specification of greater than -1 LSB guaran-

tees no missing codes and a monotonic transfer func-

tion. For example, -0.9 LSB guarantees no missing code

while -1.1 LSB results in missing code.

Offset Error

For the MAX11044/MAX11045/MAX11046, the offset

error is defined at code transition 0x8000 to 0x8001 in

offset binary encoding and 0x0000 to 0x0001 for two’s

complement encoding. The offset code transitions

should occur with an analog input voltage of exactly 0.5

is defined as the deviation between the actual analog

input voltage required to produce the offset code transi-

tion and the ideal analog input of 0.5 x (10/4.096) x

Gain Error

Gain error is defined as the difference between the

change in analog input voltage required to produce a top

code transition minus a bottom code transition, subtract-

ed from the ideal change in analog input voltage on

MAX11044/MAX11045/MAX11046, top code transition is

0x7FFE to 0x7FFF in two’s complement mode and

0xFFFE to 0xFFFF in offset binary mode. The bottom code

transition is 0x8000 and 0x8001 in two’s complement

-FS

7FFF

0001

0000

8000

8001

FFFE

INPUT VOLTAGE (LSB)

FFFF

0

FULL-SCALE

TRANSITION

ZS = 0

+FS

+FS - 1.5 x LSB

-FS + 0.5 x LSB

7FFE

+FS =

-FS =

4.096

4.096

LSB =

+FS - (-FS)

65,536

CODE =

4.096

5

Figure 8. Two’s Complement Transfer Function

FULL-SCALE

TRANSITION

+FS =

5 x VREF

4.096

ZS =

-5 x VREF

4.096

LSB =

+FS - (-FS)

65,536

VIN x 32,768

VREFIO

CODE =

+ 32,768

4.096

5

-FS

FFFF

8001

8000

0000

0001

7FFE

INPUT VOLTAGE (LSB)

7FFF

0

+FS

+FS - 1.5 x LSB

-FS + 0.5 x LSB

FFFE

Figure 9. Offset-Binary Transfer Function

4-/6-/8-Channel, 16-Bit,

Simultaneous-Sampling ADCs

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