DAC7718 datasheet(49/60 Pages) TI

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DAC7718

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SBAS467A – MAY 2009 – REVISED DECEMBER 2009

INTERNAL REGISTERS

The DAC7718 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data

Registers, the Zero Registers, the DAC Data Registers, and the Gain Registers, and are described in the

following section.

The Configuration Register specifies which actions are performed by the device. Table 11 shows the details.

Table 11. Configuration Register (Default = 800h)

DEFAULT

BIT

NAME

VALUE

DESCRIPTION

A/B bit.

When A/B = '0', reading DAC-x returns the value in the Input Data Register.

D15

A/B

When A/B = '1', reading DAC-x returns the value in the DAC Data Register.

When the correction engine is enabled, the data returned from the Input Data Register is the original data written to the

bus, and the value in the DAC Data Register is the corrected data.

Synchronously update DACs bit.

When LDAC is tied high, setting LD = '1' at any time after the write operation and the correction process complete

synchronously updates all DAC latches with the content of the corresponding DAC Data Register, and sets VOUT to a new

level. The DAC7718 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the

D14

LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After

updating, the bit returns to '0'. When the correction engine is turned off, bit LD can be set to '1' any time after the writing

operation is complete; the DAC latch is immediately updated when bit LD is set. When the LDAC pin is tied low, this bit is

ignored.

Software reset bit.

D13

RST

Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit

returns to '0'.

Power-down bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3).

Setting the PD-A bit to '1' places Group A (DAC-0, DAC-1, DAC-2, and DAC-3) into power-down operation. All output

D12

PD-A

buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-A through an internal 15-kΩ resistor. The interface is

still active.

Setting the PD-A bit to '0' returns group A to normal operation.

Power-down bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7).

Setting the PD-B bit to '1' places Group B (DAC-4, DAC-5, DAC-6, and DAC-7) into power-down operation. All output

D11

PD-B

buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-B through an internal 15-kΩ resistor. The interface is

still active.

Setting the PD-B bit to '0' returns group B to normal operation.

System-calibration enable bit.

Set the SCE bit to '1' to enable the correction engine. When the engine is enabled, the input data are adjusted by the

correction engine according to the contents of the corresponding Gain Register and Zero Register. The results are

transferred to the corresponding DAC Data Register, and finally loaded into the DAC latch, which sets the VOUT-x pin

D10

SCE

output level.

Set the SCE bit to '0' to turn off the correction engine. When the engine is turned off, the input data are transferred to the

corresponding DAC Data Register immediately, and then loaded into the DAC latch, which sets the output voltage. Refer

to the User Calibration for Zero-Code Error and Gain Error section for details.

—

Reserved. Writing to this bit has no effect; reading this bit returns '0'.

Gain bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3). Updating this bit to a new value automatically resets the Offset

DAC-A Register to the factory-trimmed value for the new gain setting.

GAIN-A

Set the GAIN-A bit to '0' for an output span = 6 × REF-A.

Set the GAIN-A bit to '1' for an output span = 4 × REF-A.

Gain bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7). Updating this bit to a new value automatically resets the Offset

DAC-B Register to the factory-trimmed value for the new gain setting.

GAIN-B

Set the GAIN-B bit to '0' for an output span = 6 × REF-B.

Set the GAIN-B bit to '1' for an output span = 4 × REF-B.

Disable SDO bit.

Set the DSDO bit to '0' to enable the SDO pin (default). The SDO pin works as a normal SPI output.

DSDO

Set the DSDO bit to '1' to disable the SDO pin. The SDO pin is always in a Hi-Z state no matter what the status of the CS

pin is.

No operation bit.

During a write operation, setting the NOP bit to '1' has no effect (the bit returns to '0' when the write operation completes).

NOP

Setting the NOP bit to '0', returns the device to normal operation.

During a read operation, the bit always returns “0”

Second wake-up operation bit.

If the WAKEUP pin is high, an alternative method to wake-up the device from sleep in SPI is by using the CS pin. When

W2 = '1', the rising edge of CS restores the device from sleep mode to normal operation, if no more than one falling edge

of SCLK exists while CS is low. However, the device will not wake up if more than one falling edge of SCLK exists. Setting

the W2 bit to '0' disables this function, and the rising edge of CS does not wake up the device.

If the WAKEUP is low, this bit is ignored and the device is always in normal mode.

D3:D0

—

Reserved. Writing to these bits has no effect; reading these bits returns '0'.

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