DAC7718 datasheet(16/60 Pages) TI

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DAC7718

SBAS467A – MAY 2009 – REVISED DECEMBER 2009

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TIMING CHARACTERISTICS: IOVDD = +5V

(1) (2) (3) (4)

At –40°C to +105°C, DVDD = +5V, and IOVDD = +5V, unless otherwise noted.

PARAMETER

MIN

MAX

UNIT

fSCLK

Clock frequency

MHz

SCLK cycle time

SCLK high time

SCLK low time

CS falling edge to SCLK falling edge setup time

SDI setup time before falling edge of SCLK

SDI hold time after falling edge of SCLK

SCLK falling edge to CS rising edge

CS high time

CS rising edge to LDAC falling edge

t10

LDAC pulse duration

t11

Delay from SCLK rising edge to SDO valid

t12

Delay from CS rising edge to SDO Hi-Z

t13

Delay from CS falling edge to SDO valid

t14

SDI to SDO delay during sleep mode

(1)

Specified by design. Not production tested.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect these parameters.

(3)

All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.

(4)

SDO loaded with 10

Ω series resistance and 10pF load capacitance for SDO timing specifications.

BLANKSPACE

TIMING CHARACTERISTICS: IOVDD = +3V

(1) (2) (3) (4)

At –40°C to +105°C, DVDD = +3V/+5V, and IOVDD = +3V, unless otherwise noted.