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SN65MLVD048 Datasheet(PDF) 11 Page - Texas Instruments |
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SN65MLVD048 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 18 page ![]() PRBSINPUT t jit(pp) VOH VOL PeaktoPeakJitter OUTPUT tc(n) tjit(per) = | tc(n) -1/fo | ACTUAL OUTPUT 1/fo IDEAL OUTPUT VOL PeriodJitter tc(n) tc(n+1) tjit(cc) = | tc(n) -tc(n+1)| CycletoCycleJitter VCC/2 CLOCKINPUT 1/fo OUTPUT VA V VB VCC/2 VA -VB VOH VOL VCC/2 V OH VOL VCC/2 VOH INPUTS VA -VB VCM 0.2Vpk Type2 0.4Vpk 1V Type1 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A. B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software. C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer. D. Period jitter and cycle-to-cycle jitter are measured using a 125-MHz 50 ± 1% duty cycle clock input. Measured over 75K samples. E. Deterministic jitter and random jitter are measured using a 250-Mbps 215 -1 PRBS input. Measured over BER = 10 -12 Figure 4. Receiver Jitter Measurement Waveforms Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :SN65MLVD048 |
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