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HT82K74EE Datasheet(PDF) 34 Page - Holtek Semiconductor Inc |
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HT82K74EE Datasheet(HTML) 34 Page - Holtek Semiconductor Inc |
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34 / 56 page ![]() HT82K74E/HT82K74EE Rev. 1.00 34 December 15, 2009 DC-to-DC Converter (DC/DC) This circuit is used to generate a stable 2.8V or 3.0V or 3.3V (error ±0.1V) power voltage for the whole device and output to the IRPT. The DC/DC clock frequency is 130kHz. It can also detect the battery voltage. If the bat- tery voltage drops to 2.2V or 2.0V, the choice of which is determined by a configuration option (error ±0.1V), the DC/DC circuit will output a Low Voltage Detect signal LVD (2.2V/2.0V Low battery flag stored in LVDF bit of the Control Register CTLR) to the MCU. There is also a low voltage reset (LVR) circuit to check the DC/DC out- put voltage. When the DC/DC output voltage drops to 2.4V, the MCU will be reset. The LVR function is con- trolled by a configuration together with a software con- trol bit named DC_ctrl in the Control Register CTLR. To enable the LVR function, the configuration option of LVR function has to be enabled and the control bit DC_ctrl must be set to ²0² to enable the DC/DC circuit. If the configuration option is selected to disable the LVR func- tion or the DC_ctrl bit is set to ²1² to disable the DC/DC circuit, then the LVR function will be disabled. If the LVR function is enabled by appropriate setting of the configu- ration option and software control bits as mentioned above, then the LVR still operates even if the MCU en- ters the Power Down Mode. It is recommended that the LVR function is enabled when the MCU is in the Power Down Mode. As the voltage of the Battery-in pin drops to 2.2V, the DC/DC converter can still operate correctly and is capa- ble of outputting a drive current of at least 50mA. Output Port used Slew Rate Control I/O Pin The I/O port output delay time of the rising and falling transition is 100ns or 200ns. There is a configuration op- tion bit to define the slew rate of all I/O pins. Amplifier Output for 27MHz The RF_OUT pin is the signal output pin and is sourced from the system oscillator clock output signal via a power amplifier. The RF_OUT impedance is 50 for which the user can design an antenna to transmit the signal. The integrated power amplifier is used to supply power to RF_OUT and can select either 0dBm for full power or -3dBm for half power, via a configuration op- tion. The amplifier can be enabled or disabled using the Amplifier function control bit AMP_ctrl in the Control Register CTLR. This output is use to output the RF signal to the antenna. Output Power= 0dBm (1 ±b) for full, -3dBm for half Load Impedance= 50 W The RF-carrier is shifted in frequency according to the data, which is known as Frequency Shift Keying (FSK). The data recognition depends upon the method which the RF receiver uses. The shifted frequency is imple- mented by the 27MHz oscillator operating mode control bit OSC_MOD in the RFCTR register. When the OSC_MOD bit is set to 1, the oscillator operates in its frequency modulation mode for RF transmission. To achieve frequency modulation, built-in capacitors can be selected which are connected to OSC1 and OSC2 using the built-in capacitor enable control bit CAP_EN in the RFCTR register. If the CAP_EN bit is set to 1, the se- lected built-in capacitors determined by the oscillator capacitor control register OSCC can be connected to OSC1 and OSC2. If the supply voltage drops lower than 3V when the oscillator operates in its frequency modula- tion mode, the oscillator current control bit I_SEL in the RFCTR register should be set to 1 to ensure that the os- cillator can perform its frequency modulation normally. D C / D C w i t h V o l t a g e D e t e c t o r B A T _ I N D C _ O u t T e s t _ D C L X 2 . 4 V L V R 1 . 8 V / 2 . 2 V / 2 . 5 V / 2 . 8 V L V D A M P . R F _ O U T S y s t e m O s c i l l o r C l o c k O u t p u t A M P _ c t r l |
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