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ST7522 Datasheet(PDF) 30 Page - Sitronix Technology Co., Ltd. |
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ST7522 Datasheet(HTML) 30 Page - Sitronix Technology Co., Ltd. |
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30 / 45 page ![]() ST7522 Ver 1.0c 30/45 2002/07/10 The V5 level be generate by OPAmp with VDD-Vcap3 power supply, so that V5 level must to be smaller than Vcap3 over –0.5V. Fine adjustment must to used EC[5:0] adjust of Electronic contrast set command. Coarse adjustment must to used jvref[1:0] adjust of Follower input voltage set command. For V5 voltage level setup formula: (follower must on of power control command) (used follower input voltage set and amplified ratio command) Jvref[1,0] [1,1] [1,0] [0,1] [0,0] Rvref 200K 400K (default) 600K 800K Rarb2 Rarb1 Rarb0 V5 amplified ratio 0 0 0 2 0 0 1 2.5 0 1 0 3 0 1 1 3.5 1 0 0 4 1 0 1 4.5 1 1 0 5(default) 1 1 1 5.5 0 1 2 3 4 5 6 7 Contrast[5,0] V5 V4 V3 V2 V1 Test condition: 1. VDD=3.0V 2. Booster/Follower=Default set 3. Bias=1/6 4. Only master chip RaRb[2:0] VDD Vcap3 VDD VSS Electric volumn EC[5:0] Reference voltage jvref[1:0] VDD V5 F (power control command) Vref [3FH-EC volume] x 20KΩ=REC The value of Vref is not allowed to be lower than 1.2V within the contrast adjustment range. Rvref 1M+REC [] x V5 amp ratio x (VSS-VDD)=V5(±5% range) Rvref 1M+REC [] x (VSS-VDD) =Vref |
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