ST7565V datasheet(63/72 Pages) SITRONIX

63 / 72 page

ST7565V

Ver 1.5b

63/72

2009/09/14

Table 25

(VDD = 2.7V, Ta = –30 to 85°C)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH8

—

Address setup time

tAW8

—

System cycle time

tCYC8

400

—

Enable L pulse width (WRITE)

tCCLW

220

—

Enable H pulse width (WRITE)

tCCHW

180

—

Enable L pulse width (READ)

tCCLR

220

—

Enable H pulse width (READ)

tCCHR

180

—

WRITE Data setup time

tDS8

—

WRITE Address hold time

tDH8

—

READ access time

tACC8

CL = 100 pF

—

140

READ Output disable time

D0 to D7

tOH8

CL = 100 pF

160

Table 26

(VDD = 1.8V, Ta = –30 to 85°C)

Rating

Item

Signal

Symbol

Condition

Min.

Max.

Units

Address hold time

tAH8

—

Address setup time

tAW8

—

System cycle time

tCYC8

640

—

Enable L pulse width (WRITE)

tCCLW

360

—

Enable H pulse width (WRITE)

tCCHW

280

—

Enable L pulse width (READ)

tCCLR

360

—

Enable H pulse width (READ)

tCCHR

280

WRITE Data setup time

tDS8

—

WRITE Address hold time

tDH8

—

READ access time

tACC8

CL = 100 pF

—

240

READ Output disable time

D0 to D7

tOH8

CL = 100 pF

520

*1 The input signal rise time and fall time (

tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(

tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

*2 All timing is specified using 20% and 80% of VDD as the reference.

tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.

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